SPARC

WIMIS

Development of wideband modem and internet switch

Project funded by:

Start date: Apr. 2017

Duration: 3 years 9 months

PROJECT OVERVIEW

wimis-cover

The project is focussed on hardware acceleration of high-end telecommunication systems. The project is divided to two major parts:

  1. Physical layer hardware implementations for satellite DVB-S2(x) and terrestrial 5G NR standards
    The major research was focussed on novel hardware architectures for quasi-cyclic LDPC decoders and encoders, as well as modulator and demodulator.
  2. Development of high-end internet switch
    The major research was on development of novel architecture and implementation of a spaceborne router integrated on an FPGA. The router supported high bit-rate satellite links: 10 Gbps satellite-to-ground links and 100 Gbps intersatellite links.

PARTICIPANTS

Lazar Saranovac

Professor

Department of Electronics

Contact

Project lead

Aleksandra Smiljanić

Professor

Department of Telecommunications

Contact

Team lead for switch development

Dragomir El Mezeni

Assistant Professor

Department of Electronics

Contact

Vladimir Petrović

Teaching & Research Assistant

Department of Electronics

Contact

Personal webpage

Strahinja Janković

Teaching & Research Assistant

Department of Electronics

Contact

Personal webpage

Marija Bežulj

Teaching & Research Assistant

Department of Electronics

Contact

Hasan Redžović

Research Assistant

Department of Telecommunications

Mihailo Vesović

Research Assistant

Department of Telecommunications

Nemanja Filipović

Ph.D. Student

Department of Electronics

Contact

PUBLICATIONS

V. L. Petrović, D. M. El Mezeni. "Reduced-Complexity Offset Min-Sum Check Node Unit for Layered 5G LDPC Decoder", Telfor Journal, Vol. 13, No. 1, pp. 7-12, Jul, 2021. DOI: 10.5937/telfor2101007P [pdf]

V. L. Petrović, D. M. El Mezeni, A. Radošević. "Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency", Electronics, Vol. 10, No. 9, p. 1106, May, 2021. IF2020: 2.397. DOI: 10.3390/electronics10091106 [pdf]

V. L. Petrović, M. M. Marković, D. M. El Mezeni, L. V. Saranovac, A. Radošević. "Flexible High Throughput QC-LDPC Decoder with Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 12, pp. 5454-5467, Dec, 2020. IF2020: 3.605. DOI: 10.1109/TCSI.2020.3018048 [pdf]

S. Janković, A. Smiljanić, M. Vesović, H. Redžović, M. Bežulj, A. Radošević, S. Moro. "High-capacity FPGA Router for Satellite Backbone Network", IEEE Transactions on Aerospace and Electronic Systems, Vol. 56, No. 4, pp. 2616-2627, Aug, 2020. IF2020: 4.102. DOI: 10.1109/TAES.2019.2951187 [pdf]

N. Filipović, D. El Mezeni, A. Radošević, "Hardware Implementation of 5G NR Deinterleaver and De-rate Matcher", 2021 15th International Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS), pp. 57-60, Niš, Serbia, Oct, 2021. DOI: 10.1109/TELSIKS52058.2021.9606247

V. Petrović, D. El Mezeni. "Reduced-Complexity Offset Min-Sum Based Layered Decoding for 5G LDPC Codes", 2020 28th Telecommunication Forum TELFOR, IEEE, pp. 109-112, Belgrade, Serbia, Nov, 2020. DOI: 10.1109/TELFOR51502.2020.9306590 [pdf]

V. Petrović, "Flexible Encoder and Decoder of Low Density Parity Check Codes", Doctoral dissertation, University of Belgrade - School of Electrical Engineering, Oct, 2021. [pdf] - in Serbian